(China (Mainland))
Product Summary
The MT48LC16M8A2TG-75:G is a high-speed CMOS, dynamic random access memory containing 134,217,728 bits. The MT48LC16M8A2TG-75:G is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4,096 rows by 1,024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
Parametrics
MT48LC16M8A2TG-75:G absolute maximum ratings: (1)Voltage on VDD/VDDQ supply relative to VSS: –1 to +4.6 V; (2)Voltage on inputs, NC or I/O pins relative to VSS: –1 to +4.6 V; (3)Operating temperature, TA: 0 to 70℃; (4)Storage temperature (plastic):–55 +150℃; (5)Power dissipation: 1W.
Features
MT48LC16M8A2TG-75:G features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths (BL): 1, 2, 4, 8, or full page; (6)Auto precharge, includes concurrent auto precharge, and auto refresh modes; (7)Self refresh mode; standard and low power; (8)64ms, 4,096-cycle refresh (commercial & industrial); (9)16ms, 4,096-cycle refresh (Automotive); (10)LVTTL-compatible inputs and outputs; (11)Single +3.3V ±0.3V power supply.
Diagrams
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 MT48LC16M8A2TG-75:G TR |
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IC SDRAM 128MBIT 133MHZ 54TSOP |
Data Sheet |
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