(China (Mainland))
Product Summary
The IC43R16800-5T is a four bank DDR DRAM organized as 2 banks x 4Mbit x 16. The IC43R16800-5T achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are ocurring on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.
Parametrics
IC43R16800-5T absolute maximum ratings: (1)Operating temperature range: 0 to 70℃; (2)Storage temperature range: -55 to 150℃; (3)VDDSupply Voltage Relative to VSS: -1V to +3.6V; (4)VDDQ Supply Voltage Relative to VSS: -1V to +3.6V; (5)VREF and Inputs Voltage Relative to VSS: -1V to +3.6V; (6)I/O Pins Voltage Relative to VSS: -0.5V to VDDQ+0.5V; (7)Power dissipation: 1.6 W; (8)Data out current (short circuit): 50 mA.
Features
IC43R16800-5T features: (1)High speed data transfer rates with system frequency up to 200 MHz; (2)Data Mask for Write Control; (3)Four Banks controlled by BA0 & BA1; (4)Programmable CAS Latency: 2, 2.5, 3; (5)Programmable Wrap Sequence: Sequential or Interleave; (6)Programmable Burst Length: 2, 4, 8 for Sequential Type, 2, 4, 8 for Interleave Type; (7)Automatic and Controlled Precharge Command; (8)Power Down Mode; (9)Auto Refresh and Self Refresh; (10)Refresh Interval: 4096 cycles/64 ms; (11)Available in 66-pin 400 mil TSOP; (12)SSTL-2 Compatible I/Os; (13)Double Data Rate (DDR); (14)Bidirectional Data Strobe (DQS) for input and output data, active on both edges; (15)On-Chip DLL aligns DQ and DQs transitions with CK transitions; (16)Differential clock inputs CK and CK.
Diagrams
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