Product Summary

The MT49H32M9FM-25 is a 288Mb reduced latency DRAM (RLDRAM II) designed for high bandwidth communication data storage elecommunications, networking, and cache applications, etc. The MT49H32M9FM-25’ 8-bank architecture is optimized for high speed and achieves a peak bandwidth of 28.8 Gb/s, using a 36-bit interface and a maximum system clock of 400 MHz. The double data rate (DDR) interface transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output data is referenced to the free-running output data clock.

Parametrics

MT49H32M9FM-25 absolute maximum ratings: (1)Storage temperature: -55 to +150℃; (2)I/O voltage: -0.3V VDDQ + 0.3 V; (3)Voltage on VEXT supply relative to VSS: -0.3 to +2.8 V; (4)Voltage on VDD supply relative to VSS: -0.3 to +2.1 V; (5)Voltage on VDDQ supply relative to VSS: -0.3 to +2.1 V; (6)Junction temperature: 110℃.

Features

MT49H32M9FM-25 features: (1)400 MHz DDR operation (800 Mb/s/pin data rate); (2)Organization, 8 Meg x 36, 16 Meg x 18, and 32 Meg x 9; (3)8 banks, Cyclic bank switching for maximum bandwidth Reduced cycle time (20ns at 400 MHz); (4)Nonmultiplexed addresses (address multiplexing option available); (5)SRAM-type interface; (6)Programmable READ latency (RL), row cycle time, and burst sequence length; (7)Balanced READ and WRITE latencies in order to optimize data bus utilization; (8)Data mask for WRITE commands; (9)Differential input clocks (CK, CK#); (10)Differential input data clocks (DKx, DKx#); (11)On-chip DLL generates CK edge-aligned data and output data clock signals; (12)Data valid signal (QVLD); (13)32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms); (14)144-ball μBGA package; (15)HSTL I/O (1.5V or 1.8V nominal); (16)25Ω-60Ω matched impedance outputs; (17)2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O; (18)On-die termination (ODT) RTT.

Diagrams

MT49H32M9FM-25 block diagram

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