(China (Mainland))
Product Summary
The MT49H32M18CHU-25E:A is a 288Mb reduced latency DRAM (RLDRAM) II designed for high bandwidth communication data storage. Applications include, but are not limited to, transmitting or receiving buffers in telecommunication systems and data or instruction cache applications requiring large amounts of memory. The MT49H32M18CHU-25E:A’s eightbank architecture is optimized for high speed and achieves a peak bandwidth of 28.8 Gb/s, using two separate 18-bit double data rate (DDR) parts and a maximum system clock of 400 MHz。
Parametrics
MT49H32M18CHU-25E:A absolute maximum ratings: (1)Storage Temperature: -55℃ to +150℃; (2)I/O Voltage: -0.3V to VDDQ + 0.3V; (3)Voltage on VEXT Supply Relative to VSS: -0.3V to +2.8V; (4)Voltage on VDD Supply Relative to VSS: -0.3V to +2.1V; (5)Voltage on VDDQ Supply Relative to VSS: -0.3V to +2.1V; (6)Junction Temperature: 110℃.
Features
MT49H32M18CHU-25E:A features: (1)288Mb; (2)400 MHz DDR operation (800 Mb/s/pin data rate); (3)Organization; (4)16 Meg x 18, 32 Meg x 9 Separate I/O; (5)8 banks; (6)Cyclic bank switching for maximum bandwidth; (7)Reduced cycle time (20ns at 400 MHz); (8)Nonmultiplexed addresses (address multiplexing option available); (9)SRAM-type interface; (10)Read latency (RL), row cycle time, and burst sequence length; (11)Balanced READ and WRITE latencies in order to optimize data bus utilization; (12)Data mask for WRITE commands; (13)Differential input clocks (CK, CK#); (14)Differential input data clocks (DKx, DKx#); (15)On-chip DLL generates CK edge-aligned data and output data clock signals; (16)Data valid signal (QVLD); (17)32ms refresh (8K refresh for each bank; 64k refresh command must be issued in total each 32ms); (18)144-ball FBGA package; (19)HSTL I/O (1.5V or 1.8V nominal); (20)25Ω-60Ωmatched impedance outputs; (21)2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O; (22)On-die termination (ODT) RTT.
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